现面向广大客户提供赛灵思（xilinx）XC95 系列CPLD芯片技术资讯及芯片解密服务。

XC9536XL，XC9572XL XC95144XL XC95288XL XC9572XV，XC9536XV XC95144(160脚），XC95144XV(160脚） XC95288 XC9572，XC9536  xc2c32，xc2c128，xc2c256

XC95288XL概述

The XC95288XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of 16 54V18 Function Blocks, providing 6400 usable gates with propagation delays of 6 ns.

XC95288XL特性

·6 ns pin-to-pin logic delays

·System frequency up to 208 MHz

·288 macrocells with 6400 usable gates

·Available in small footprint packages

- 144-pin TQFP (117 user I/O pins)

- 208-pin PQFP (168 user I/O pins)

- 256-pin BGA (192 user I/O pins)

- 256-pin FBGA (192 user I/O pins)

- 280-CSP (192 user I/O pins)

- Pb-free available for all packages

·Optimized for high-performance 3.3V systems

- Low power operation

- 5V tolerant I/O pins accept 5 V, 3.3V, and 2.5V signals

- 3.3V or 2.5V output capability

- Advanced 0.35 micron feature size CMOS Fast FLASHTM technology

·Advanced system features

- In-system programmable

- Superior pin-locking and routability with Fast CONNECTTM II switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with individual product-term allocation

- Local clock inversion with three global and one product-term clocks

- Individual output enable per output pin with local inversion

- Input hysteresis on all user and boundary-scan pin inputs

- Bus-hold circuitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

·Fast concurrent programming

·Slew rate control on individual outputs

·Enhanced data security features

·Excellent quality and reliability

- Endurance exceeding 10,000 program/erase cycles

- 20 year data retention

- ESD protection exceeding 2,000V

·Pin-compatible with 5V-core XC95288 device in the 208-pin HQFP package

WARNING: Programming temperature range of TA = 0℃ to +70℃